1. Field of the Invention
The present invention relates to a method of manufacturing a nonvolatile semiconductor memory, such as a NAND nonvolatile semiconductor memory.
2. Background Art
In the memory cell part of a conventional nonvolatile semiconductor memory, device regions and device isolation regions are formed in a line and space pattern having a pitch of 2F, supposing that the design rule is F. A plurality of memory cell transistors are formed in a line and space pattern having the same pitch of 2F perpendicularly to the line and space pattern of the device regions and device isolation regions.
Select transistors are formed on the opposite sides of the memory cell transistors. Contacts connected to the device regions are formed between adjacent select transistors. The contacts include contacts that serve as a bit line contact and contacts that are connected to each other by wiring on the top thereof and serve as a source line.
In regions of the select transistors and a peripheral transistor, an opening is formed in an insulating film (inter-poly dielectric (IPD) film), through which the floating gate and the control gate are electrically connected to each other.
To establish this connection, a method of forming the opening before forming the control gate or a method of forming the opening after forming the control gate can be used (see Japanese Patent Laid-Open Publication No. 2005-123524, for example).
According to the conventional method described above, for example, when the distance between adjacent contacts decreases as the NAND nonvolatile semiconductor memory becomes smaller, the possibility of a short circuit between the bit line contacts increases. If the contact diameter is reduced to prevent the short circuit, the margin for lithography for forming the contact pattern is reduced. In addition, there is a problem that the contact resistance increases because the contact area between the contact and the device region decreases.
To solve the problem, there has been proposed a method of adequate distance between adjacent contacts by arranging the contacts in a zigzag pattern.
However, this method requires a margin for preventing a short circuit between the select transistors and the contacts. Therefore, the distance between the select transistors has to be increased, and as a result, the chip size increases.
Alternatively, there has been proposed a method of forming a source line separately from a bit line contact (see Japanese Patent Laid-Open Publication No. 2002-231835 and, for example). Prior to formation of a bit line contact, a pattern is formed in an additional lithography step, an interlayer insulating film is etched to form a groove extending to a device region, and a conductive material is embedded in the groove. In this way, a source line is formed in advance. Then, an additional interlayer insulating film is stacked thereon to form a bit line contact.
In this case, the distance between the select transistors on the side of the source line can be smaller than the distance between the select transistors on the side of the bit line, and therefore, the increase of the chip size can be prevented.
However, the conventional method has a problem that the manufacturing cost increases because the method requires an additional step of forming the source line.